Data (Pixel) Stream Interface
The Data Stream interface is based on the AMBA AXI4-Stream Protocol Specification:
□ | At the source side, this interface provides the CustomLogic with images acquired from a CoaXPress Device (for example a CoaXPress camera) |
□ | At the destination side, the Data Stream interface transfers the resulting images/data generated by the CustomLogic to the PCI Express DMA Back-End channel. |

Signal |
Direction |
Description |
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axis_tvalid_in |
IN |
TVALID indicates that the source is driving a valid transfer. A transfer takes place when both TVALID and TREADY are asserted. |
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axis_tready_in |
OUT |
TREADY indicates that the CustomLogic can accept a transfer in the current cycle. |
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axis_tdata_in [*] |
IN |
TDATA is the primary payload that is used to provide the data passing across the interface. |
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axis_tuser_in [3:0] |
IN |
TUSER is user defined sideband information that can be transmitted alongside the data stream. The TUSER content is encoded as follows:
|

Signal |
Direction |
Description |
||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
axis_tvalid_out |
OUT |
TVALID indicates that the CustomLogic is driving a valid transfer. A transfer takes place when both TVALID and TREADY are asserted. |
||||||||||||
axis_tready_out |
IN |
TREADY indicates that the PCI Express DMA Back-End can accept a transfer in the current cycle. |
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axis_tdata_out [*] |
OUT |
TDATA is the primary payload that is used to provide the data passing across the interface. |
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axis_tuser_out [3:0] |
OUT |
TUSER is user defined sideband information that can be transmitted alongside the data stream. The TUSER content is encoded as follows:
|
At the CustomLogic destination side, the axis_tuser_out signal has the function of controlling the PCI Express DMA Back-End. The flags carried by the axis_tuser_out are interpreted as follows:
□ | Start-of-Buffer: A cycle containing this flag starts a new buffer. |
□ | End-of-Buffer: A cycle containing this flag ends a buffer even if it still has available space to accommodate new transfers. |

TVALID/TREADY handshake and TUSER flags timing diagram
In this example, we consider that the LinePitch is 64 bytes (4 transfer cycles of 16 bytes each) and the full frame is composed of 10 lines/packet.
For more information about the AXI4-Stream Protocol, please refer to Xilinx “AXI Reference Guide (UG1037)” at www.xilinx.com and “AMBA AXI4-Stream Protocol Specification” at www.amba.com.