DDR4 Memory Interface

The DDR4 on-bard memory interface is based on the AMBA AXI4-Stream Protocol Specification.

The AXI4 is a memory-mapped interface that consists of five channels:

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Write Address Channel

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Write Data Channel

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Write Response Channel

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Read Address Channel

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Read Data Channel

Data can move in both directions between the master and slave simultaneously, and data transfer sizes can vary. The limit in AXI4 is a burst transaction of up to 256 data transfers.

AXI4 signals description

The following sections briefly describe the AXI4 signals.

For a complete view of signal, interface requirements and transaction attributes, please refer to AMBA AXI and ACE Protocol Specification document at www.amba.com.

Master interface global signals

Signal	Width	Direction	Description
m_axi_resetn	1	Input	RESETn resets the AXI4 interface.

Master write address channel interface signals

Signal

Width

Direction

Description

m_axi_awaddr

Output

Write address. The write address gives the address of the first transfer in a write burst transaction.

m_axi_awlen

Output

Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.

Burst_Length = AWLEN[7:0] + 1

m_axi_awsize

Output

Burst size. This signal indicates the size of each transfer in the burst.

Burst_Size = 2^AWSIZE[2:0]

m_axi_awburst

Output

Burst type. The burst type and the size information, determine how the address for each transfer within the burst is calculated.

Burst_Type: "00" = FIXED; "01" = INCR; "10" = WRAP

m_axi_awlock

Output

Lock type. Provides additional information about the atomic characteristics of the transfer.

Atomic_Access: '0' Normal; '1' Exclusive

m_axi_awcache

Output

Memory type. This signal indicates how transactions are required to progress through a system.

Memory_Attributes:

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AWCACHE[0] Bufferable

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AWCACHE[1] Cacheable

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AWCACHE[2] Read-allocate

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AWCACHE[3] Write-allocate

m_axi_awprot

Output

Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.

Access_Permissions:

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AWPROT[0] Privileged

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AWPROT[1] Non-secure

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AWPROT[2] Instruction

m_axi_awqos

Output

Quality of Service, QoS. The QoS identifier sent for each write transaction.

Quality_of_Service: Priority level

m_axi_awvalid

Output

Write address valid. This signal indicates that the channel is signaling valid write address and control information.

m_axi_awready

Input

Write address ready. This signal indicates that the slave is ready to accept an address and associated control signals.

The descriptions are excerpts from AMBA AXI and ACE Protocol Specification.

Master write data channel interface signals

Signal	Width	Direction	Description
m_axi_wdata	W	Output	Write data.
m_axi_wstrb	W/8	Output	Write strobes. This signal indicates which byte lanes hold valid data. There is one write strobe bit for each eight bits of the write data bus.
m_axi_wlast	1	Output	Write last. This signal indicates the last transfer in a write burst.
m_axi_wvalid	1	Output	Write valid. This signal indicates that valid write data and strobes are available.
m_axi_wready	1	Input	Write ready. This signal indicates that the slave can accept the write data.

NOTE

In the Width column: "W" refers to MEMORY_DATA_WIDTH, the data width of the write data channel.

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3602 Coaxlink Octo (1-camera, custom-logic) => W = 128 ;

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3603 Coaxlink Quad CXP-12(1-camera, custom-logic) => W = 256;

□

3603 Coaxlink Quad CXP-12 (4-camera, custom-logic) => W = 256;

The descriptions are excerpts from AMBA AXI and ACE Protocol Specification.

Master write response channel interface signals

Signal

Width

Direction

Description

m_axi_bresp

Input

Write response. This signal indicates the status of the write transaction.

Response:

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"00" = OKAY

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"01" = EXOKAY

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"10" = SLVERR

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"11" = DECERR

m_axi_bvalid

Input

Write response valid. This signal indicates that the channel is signaling a valid write response.

m_axi_bready

Output

Response ready. This signal indicates that the master can accept a write response.

The descriptions are excerpts from AMBA AXI and ACE Protocol Specification.

For m_axi_bresp:

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OKAY: Normal access success. Indicates that a normal access has been successful. Can also indicate an exclusive access has failed. See OKAY, normal access success.

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EXOKAY: Exclusive access okay. Indicates that either the read or write portion of an exclusive access has been successful.

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SLVERR: Slave error. Used when the access has reached the slave successfully, but the slave wishes to return an error condition to the originating master.

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DECERR: Decode error. Generated, typically by an interconnect component, to indicate that there is no slave at the transaction address.

Master read address channel interface signals

Signal

Width

Direction

Description

m_axi_araddr

Output

Read address. The read address gives the address of the first transfer in a read burst transaction.

m_axi_arlen

Output

Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.

Burst_Length = ARLEN[7:0] + 1

m_axi_arsize

Output

Burst size. This signal indicates the size of each transfer in the burst.

Burst_Size = 2^ARSIZE[2:0]

m_axi_arburst

Output

Burst type. The burst type and the size information, determine how the address for each transfer within the burst is calculated.

Burst_Type: "00" = FIXED; "01" = INCR; "10" = WRAP

m_axi_arlock

Output

Lock type. Provides additional information about the atomic characteristics of the transfer.

Atomic_Access: '0' Normal; '1' Exclusive

m_axi_arcache

Output

Memory type. This signal indicates how transactions are required to progress through a system.

Memory_Attributes:

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ARCACHE[0] Bufferable

□

ARCACHE[1] Cacheable

□

ARCACHE[2] Read-allocate

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ARCACHE[3] Write-allocate

m_axi_arprot

Output

Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.

Access_Permissions:

□

ARPROT[0] Privileged

□

ARPROT[1] Non-secure

□

ARPROT[2] Instruction

m_axi_arqos

Output

Quality of Service, QoS. The QoS identifier sent for each write transaction.

Quality_of_Service: Priority level

m_axi_arvalid

Output

Read address valid. This signal indicates that the channel is signaling valid read address and control information.

m_axi_arready

Input

Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals.

The descriptions are excerpts from AMBA AXI and ACE Protocol Specification.

Master read data channel interface signals

Signal	Width	Direction	Description
m_axi_rdata	W	Input	Read data.
m_axi_rresp	2	Input	Read response. This signal indicates the status of the read transfer. Response: "00" = OKAY; "01" = EXOKAY; "10" = SLVERR; “11” = DECERR
m_axi_rlast	1	Input	Read last. This signal indicates the last transfer in a read burst.
m_axi_rvalid	1	Input	Read valid. This signal indicates that the channel is signaling the required read data.
m_axi_rready	1	Output	Read ready. This signal indicates that the master can accept the read data and response information.

NOTE

In the Width column: "W" refers to MEMORY_DATA_WIDTH, the data width of the write data channel.

□

3602 Coaxlink Octo (1-camera, custom-logic) => W = 128 ;

□

3603 Coaxlink Quad CXP-12(1-camera, custom-logic) => W = 256;

□

3603 Coaxlink Quad CXP-12 (4-camera, custom-logic) => W = 256;

The descriptions are excerpts from AMBA AXI and ACE Protocol Specification.