Reference Design Build Procedure
To build the reference design:
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1.
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Decompress the package in a folder respecting Vivado requirements (no special characters in the path). For example: c:/workspace/CustomLogic |
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3.
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Execute the script "create_vivado_project.tcl" in the Tcl Console.
TCL command: source c:/workspace/CustomLogic/03_scripts/create_vivado_project.tcl
As result, a Vivado project is created at the folder 07_vivado_project. For example: c:/workspace/CustomLogic/07_vivado_project. |
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4.
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Run Implementation.
TCL command: launch_runs impl_1 |
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5.
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Execute the script "customlogic_functions.tcl" in the Tcl Console.
TCL command: source c:/workspace/CustomLogic/03_scripts/customlogic_functions.tcl
This script makes the following two functions available: |
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□
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customlogic_bitgen: Generate .bit file. |
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customlogic_prog_fpga: Program FPGA via JTAG (volatile). |
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6.
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After completion of the implementation, run the function “customlogic_bitgen” in the TCL console.
TCL command: customlogic_bitgen
This function updates the bitstream file in the folder 06_release. |
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7.
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After the bitstream is generated, update the FPGA by executing the function customlogic_prog_fpga in the TCL console.
TCL command: customlogic_prog_fpga |
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This function requires a Xilinx JTAG programmer. |
