Pixel Data Processing

This operation extracts individual pixel components data from the CoaXPress image data bit stream according to the bit depth – input-bit-depth – specified by the 'PixelF' property of the CoaXPress Image Header.

All components have the same pixel bit depth. Possible values are 8-/10-/12-/14- and 16-bit.

The slicer delivers, for each image line, all the pixel components necessary to build a number of pixels specified by the 'Xsize' property of the CoaXPress Image Header.

The slicer discards CoaXPress line-padding data.

This operation applies a linear gain and offset transformation to each individual pixel components.

For more information and configuration instructions, refer to Flat Field Correction .

This operation applies a lookup table transformation to each individual pixel components.

For more information and configuration instructions, refer to Lookup Table Processing .

This operation transforms the raw Bayer CFA data stream issued by the camera into an RGB color data stream.

For more information and configuration instructions, refer toBayer CFA Decoding .

This operation unpacks 10-bit, 12-bit, and 14-bit pixel components to 8-bit or 16-bit.

It can be disabled for monochrome and Bayer CFA pixel formats.

For more information and configuration instructions, refer toPixel Component Unpacking.

This operation modifies the component order of multi-components pixel data.

For more information and configuration instructions, refer to Pixel Component Re-Ordering.

This operation modifies the byte order of 16-bit pixel component data.

For more information, refer to Endianness Conversion.

This operation builds concatenates the components data of all pixels of an image line:

This operation appends padding bits or bytes to the image line data to reach the next alignment-boundary required by the hardware implementation.

The alignment boundary requirements are product-specific, for instance:

The pixel processor sustain the highest camera pixel rate. Unless specified otherwise, all the above operations are executed while transferring data to the GenTL with a negligible latency.

PCI Express Bandwidth Limitation

When acquiring pixels having a pixel bit depth larger than 8-bit, each pixel is expanded to 16-bit. In these cases, the PCI Express bandwidth limitation of the Host PC may negatively impact the achievable frame- or line-rate.

On-board Memory Bandwidth Limitation

For FFC use cases, the on-board memory bandwidth is not sufficient to sustain the full CoaXpress data rate.