FIFO Buffer
DRAM Memory Size per Product
| Product | DRAM Memory Size |
|---|---|
|
|
512 MB |
|
|
512 MB |
|
|
1 GB |
|
|
1 GB |
|
|
1 GB |
|
|
512 MB |
|
|
1 GB |
|
|
1 GB |
|
|
512 MB |
|
|
2 GB |
|
|
2 GB |
The DRAM memory is partitioned according to the installed firmware variants.
| ● | All firmware variants allocate one partition named FIFO Buffer for each stream of each device. |
| ● | The firmware variants supporting FFC allocate one partition for the storage of gain and offset coefficients |
Refer to Firmware Variants per Product for the available buffer size per data stream and per device.
Fifo Buffer Operation
The Fifo Buffer operates as a FIFO to decouple the CoaXPress data flow from the Pixel Processing and the PCI Express data flow.
It absorbs temporary dropouts of the PCI Express data flow ensuring a reliable CoaXPress data acquisition.
It enables burst-mode CoaXPress data acquisition at the highest data rates regardless the limits of the Pixel Processor and the PCI Express interface.
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