TTL Input/5V CMOS Output
Applies to:
TTL Input/5V CMOS Output Simplified schematic
The port implements a 5V CMOS driver and a TTL-compliant receiver.
DC characteristics
Parameter | Conditions | Min. | Typ. | Max. | Units |
---|---|---|---|---|---|
ESD protection | Human Body Model (HBM) | 2 | kV |
Note: The I/O port includes a latch-up protection.
Driver
Parameter | Conditions | Min. | Typ. | Max. | Units |
---|---|---|---|---|---|
Absolute maximum voltage rating | 0 | 5 | V | ||
Low-level output current | 24 | mA | |||
Low-level output voltage | @50µA | 0.001 | 0.1 | V | |
@ 24 mA | 0.81 | V | |||
High-level output current | -24 | mA | |||
High-level output voltage | @-50 µA; (1) | 4.9 | 4.99 | V | |
@-24 mA; (1) | 3.89 | V |
Condition (1): 300 Ohms line termination resistor to GND.
Receiver
Parameter | Conditions | Min. | Typ. | Max. | Units |
---|---|---|---|---|---|
Absolute maximum voltage rating | 0 | 5 | V |
AC characteristics
Driver
Parameter | Conditions | Min. | Typ. | Max. | Units |
---|---|---|---|---|---|
Pulse width | 500 | ns | |||
Pulse rate | 0 | 1 | MHz | ||
10%-90% rise/fall time | TBD | ns |
Receiver
Parameter | Conditions | Min. | Typ. | Max. | Units |
---|---|---|---|---|---|
Pulse width | 500 | ns | |||
Pulse rate | 0 | 1 | MHz | ||
10%-90% rise/fall time | TBD | ns |
Logical Map
The state of the port is reported as follows:
Input voltage | Logical State |
---|---|
VIN > 2.0 V | HIGH |
VIN < 0.8 V | LOW |
Unconnected input port | Undetermined |
Compatible sources
Sources with the following drivers are compatible:
□ | LVTTL ( 3.3 V low-voltage TTL) |
□ | CMOS (5V CMOS) |
□ | LVCMOS (3.3V CMOS) |
Compatible loads
Loads with the following receivers are compatible:
□ | TTL (5 V TTL) |
□ | CMOS (5V CMOS) |