PCI Interface

PCI Identification

Grablink cards are identified on the PCI bus as follows:

 

PCI Vendor ID

 0x10B5 0x1805

0x1805

0x1805

0x1805

0x1805

PCI Device ID

 0x2491 (9361) 0x307 (775)

0x030E (782)

0x030C (780)

0x030A (778)

0x0310 (784)

PCI Device ID (Recovery mode)

 N/A N/A

0x030F (783)

0x030D (781)

0x030B (779)

0x0311 (785)

PCI Sub-Vendor ID

 0x0000 0x0000

0x0000

0x0000

0x0000

0x0000

PCI Sub-Device ID

 0x0001 0x0001

0x0001

0x0001

0x0001

0x0001

PCI Interface Type per Product

Product Interface Type

1191 Grablink Value

32-bit, 33 MHz, conventional PCI

1621 Grablink Express

1-lane Rev 1.1 PCI Express End-point

1624 Grablink Base

1-lane Rev 1.1 PCI Express End-point

1623 Grablink DualBase

4-lane Rev 1.1 PCI Express End-point

1622 Grablink Full

4-lane Rev 1.1 PCI Express End-point

1626 Grablink Full XR

4-lane Rev 1.1 PCI Express End-point

Applies to:

The 32-bit, 33 MHz conventional PCI interface::

● complies with revision 2.3 of the PCI Local Bus specification,
● has a 32-bit wide connector,
● operates at a maximum of 33 MHz,
● accepts 3 V or 5 V signaling.

The card can be used in a 32-bit or 64-bit PCI slot with any signaling.

The card can be used in a 33 MHz or 66 MHz PCI slot as well as in a 66 MHz, 100 MHz or 133 MHz PCI-X slot.

Installing the board on a 66 MHz or faster bus will restrict the bus to Conventional PCI at 66 MHz for all agents installed on this bus.

As per the PCI Local Bus specification, revision 2.3, the following power supplies are mandatory on the motherboard PCI connectors: +3.3 V, +5 V, +12 V and -12V.

Applies to:

The 1-lane Rev 1.1 PCI Express end-point:

● complies with revision 1.1 of the PCI Express Card Electromechanical specification,
● has a 1-lane wide connector,
● operates at 2.5 GHz,
● supports payload size up to 1024 bytes,
● supports 64-bit addressing for bus master access.

The card can be used in any 1-lane , 4-lane or 8-lane PCIe slot. It can be also be used in a 16-lane PCIe slot that is not reserved for a graphical board.

Payload Size

During the configuration of the PCI Express fabric, the PCI Express end point interface negotiates the payload size of the TLP packets. The maximum payload size of the end point interface is 1024 bytes. The negotiated payload size is reported through the MultiCam parameter PCIePayloadSize. Possible values are 128,256, 512 and 1024.

PCIe Endpoint Interface Revision Number

The revision number of the PCI Express end point interface is reported through the MultiCam PCIeEndpointRevisionID parameter.

Applies to:

The 4-lane Rev 1.1 PCI Express end-point:

● complies with revision 1.1 of the PCI Express Card Electromechanical specification,
● has a 4-lane wide connector,
● operates at 2.5 GHz,
● supports payload size up to 1024 bytes,
● supports 64-bit addressing for bus master access,
● supports 1-lane and 4-lane link widths (see table),
● allows for logical reversal of lane numbers (see table),
● offers the optimal performance when it is configured for 4-lane operation.

The card can be used in any 1-lane , 4-lane or 8-lane PCIe slot. It can be also be used in a 16-lane PCIe slot that is not reserved for a graphical board.

Lanes Configuration

During the configuration of the PCI Express fabric, the PCI Express end point interface negotiates the link width. The negotiated link width is reported through the PCIeLinkWidth parameter. This PCI Express end point interface supports two values of link width: 1 and 4.

The width of 4 is selected when the board is plugged into a slot a having one of the two supported 4-lane configuration. In any other case, the selected width is 1.

The 4-lane PCI Express end point interface implements lane reversal, which enables the logical reversal of lane numbers.

Lane configuration

Physical lane 3

Physical lane 2

Physical lane 1

Physical lane 0

Four non-reversed lanes

Logical lane 3

Logical lane 2

Logical lane 1

Logical lane 0

Four reversed lanes starting on lane 3

Logical lane 0

Logical lane 1

Logical lane 2

Logical lane 3

One non-reversed lane

 

 

 

Logical lane 0

One non-reversed lane starting on lane 3

Logical lane 0

 

 

 

Payload Size

During the configuration of the PCI Express fabric, the PCI Express end point interface negotiates the payload size of the TLP packets. The maximum payload size of the end point interface is 1024 bytes. The negotiated payload size is reported through the MultiCam parameter PCIePayloadSize. Possible values are 128,256, 512 and 1024.

PCIe Endpoint Interface Revision Number

The revision number of the PCI Express end point interface is reported through the MultiCam PCIeEndpointRevisionID parameter.

PCIe end-point to PC memory data transfer performance

Parameter Conditions Min. Typ. Max. Unit
Sustainable output data rate 4-lane @ 2.5 GT/s   800   MB/s