Data (Pixel) Stream Interface

The Data Stream interface is based on the AMBA AXI4-Stream Protocol Specification:

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At the slave side, the CustomLogic receives images acquired from a CoaXPress Device (for example a CoaXPress camera)

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At the master side, the Data Stream interface transfers the resulting images/data generated by the CustomLogic to the PCI Express DMA Back-End channel.

Slave interface signals

Signal

Width

Direction

Description

s_axis_aresetn

N*1

Input

ARESETn resets the AXI4-Stream interface.
This pulse is asserted when a Stop Acquisition command (DSStopAcquisition) is executed.
This signal should be used to clear the CustomLogic internal Data Stream pipeline.

s_axis_tvalid

N*1

Input

TVALID indicates that a corresponding master interface is driving a valid transfer.
A transfer takes place when both TVALID and TREADY are asserted.

s_axis_tready

N*1

Output

TREADY indicates that the CustomLogic can accept a transfer in the current cycle.

s_axis_tdata

N*W

Input

TDATA is the primary payload that is used to provide the data passing across the interface.

s_axis_tuser

N*4

Input

TUSER is user defined sideband information that can be transmitted alongside the data stream.
The TUSER content is encoded as follows:

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TUSER [0] => Start-of-Frame (SOF)

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TUSER [1] => Start-of-Line (SOL)

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TUSER [2] => End-of-Line (EOL)

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TUSER [3] => End-of-Frame (EOF)

NOTE

In the Width column: “N” refers to the total number of interface slots, which is the number of devices/cameras supported by the CustomLogic variant, and "W" refers to STREAM_DATA_WIDTH, the stream data width per device/camera.

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3602 Coaxlink Octo (1-camera, custom-logic) => N = 1; W = 128 ;

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3603 Coaxlink Quad CXP-12 (1-camera, custom-logic) => N = 1; W = 256;

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3603 Coaxlink Quad CXP-12 (4-camera, custom-logic) => N = 4; W = 64;

Master interface signals

Signal

Width

Direction

Description

m_axis_tvalid

N*1

Output

TVALID indicates that the CustomLogic is driving a valid transfer.
A transfer takes place when both TVALID and TREADY are asserted.

m_axis_tready

N*1

Input

TREADY indicates that the PCI Express DMA Back-End can accept a transfer in the current cycle.

m_axis_tdata

N*W

Output

TDATA is the primary payload that is used to provide the data passing across the interface.

m_axis_tuser

N*4

Output

TUSER is user defined sideband information that can be transmitted alongside the data stream. The TUSER content is encoded as follows:

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axis_tuser_out[0] => Start-of-Buffer (SOB)

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axis_tuser_out[1] => Reserved

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axis_tuser_out[2] => Reserved

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axis_tuser_out[3] => End-of-Buffer (EOB)

NOTE

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3602 Coaxlink Octo (1-camera, custom-logic) => N = 1; W = 128 ;

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3603 Coaxlink Quad CXP-12 (1-camera, custom-logic) => N = 1; W = 256;

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3603 Coaxlink Quad CXP-12 (4-camera, custom-logic) => N = 4; W = 64;

NOTE

At the CustomLogic master side, the m_axis_tuser signal has the function of controlling the PCI Express DMA Back-End. The flags carried by m_axis_tuser are interpreted as follows:

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Start-of-Buffer: A cycle containing this flag starts a new buffer.

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End-of-Buffer: A cycle containing this flag ends a buffer even if it still has available space to accommodate new transfers.