4-lane Rev 2.0 PCIe end-point

Applies to Closed1628 Grablink Duo, 1629 Coaxlink Duo PCIe/104-EMB, 1630 Coaxlink Mono, 1631 Coaxlink Duo, 1632 Coaxlink Quad and 1637 Coaxlink Quad 3D-LLE.

The PCI Express Interface implements a PCIe end-point interface and provides electrical power to the on-board circuits.

The 4-lane Rev 2.0 PCIe end-point:

● complies with Revision 2.0 of the PCI Express Card Electromechanical specification,
● supports 1-lane, 2-lane, and 4-lane link width,
● supports PCIe Rev 2.0 link speed (5.0 GT/s with 8b/10b coding),
● supports PCIe Rev 1.0 link speed (2.5 GT/s with 8b/10b coding),
● supports payload size up to 512 bytes,
● offers the optimal performance when it is configured for 4-lane PCIe Rev 2.0 link speed (5 GT/s).

4-lane Rev 2.0 PCIe end-point to PC memory data transfer performance

Parameter Conditions Min. Typ. Max. Unit
Sustainable output data rate

4-lane @ 5 GT/s (PCIe Rev 2.0)

   1,700   MB/s
4-lane @ 2.5 GT/s (PCIe Rev 1.0)   800   MB/s

2-lane @ 5 GT/s (PCIe Rev 2.0)

   800  

MB/s