Camera Link ECCO-85 Host Interface

Applies to Closed1628 Grablink Duo.

 

The Camera Link ECCO-85 Host Interface of 1628 Grablink Duo implements a Camera Link Host interface for 2 Base configuration cameras or 1 Medium/Full,72-bit or 80-bit configurations camera.

FPGA emulated Channel Link receivers

The interface emulates Channel Link receivers with an FPGA according to the Camera Link 2.1 standard

Each channel link receiver is composed of:

● 5 high-performance LVDS inputs terminated with a 100 Ohm resistor: one clock and 4 serialized data inputs.
● a digital PLL for clock recovery and clock jitter cancellation
● a dynamic pair-to-pair skew compensator
● 4 7:1 data de-serializers

Extended Camera Link Cable Operation - ECCO

The FPGA emulated Channel Link exceeds the performance of original Channel Link by:

● reducing the requirements for the cable pair-to-pair skew
● allowing longer cables

See also: ECCO ( Extended Camera Link Cable Operation) jitter and cable skew compensation

Requirements for cameras:

● Clock frequency range: 20 MHz up to 85 MHz
● The clock may not be switched off during normal operation.
● The clock jitter must be as low as possible; it is recommended to use crystal oscillators to generate the Camera Link clock. It may not exceed 1 ns or 20% of the clock period.
● The clock duty cycle must be better than 25%/75%.
● For correct operation of PoCL, it is mandatory to apply the clock as soon as possible after power on. The time-out delay is 500 milliseconds.
● The electrical signal of the 4 data lines must be conform to the Camera Link requirements.

Additional requirements for Medium/Full/72-bit/80-bit cameras

● The Camera Link standard specifies that all four enable signals (LVAL, FVAL, DVAL, SPARE) are supplied to all Channel Links. However, for the 80-bit configuration, only the LVAL signal needs to be distributed on the second and the third channel link.
● The same LVAL signal must be applied on all Channel Links
● At least one valid LVAL pulse needs to be sent to the frame grabber before it can start acquiring data.
● The skew across LVAL signals of all channel link receivers involved in the configuration may not exceed 2 ns (about 40 cm of cable). It is recommended to:
□ Use identical cables in terms of length and propagation delay characteristic for both connectors.
□ Apply the LVAL signal when power is on.

Line drivers/receivers

All output lines (Camera Control lines (CC1 to CC4) and SERTC COM line) comply with the LVDS driver specification.

All input lines (Channel Link lines and SERTFG COM line) are terminated with a 100 Ohm impedance and comply with the LVDS receiver specification.

All lines are protected against over-voltage and electrostatic discharges

Switchable configuration

The Camera Link interface of 1628 Grablink Duo has 2 configurations. Eleven pairs of pins of the Camera Link B connector change their function according to the configuration:

Pin pairs

1-camera

Medium/72-bit/Full/80-bit configuration

2-camera

Base configuration

 Direction Change
3, 16 ZCLK - Channel Link Z - Clock - Input CC3 - Camera Control 3 - Output Yes
6,19 Z0 - Channel Link Z - Data 0 - Input SERTFG -Serial COM - Input  
5, 18 Z1 - Channel Link Z - Data 1 - Input CC1 - Camera Control 1 - Output Yes
4, 17 Z2 - Channel Link Z - Data 2 - Input CC2 - Camera Control 2 - Output Yes
2,15 Z3 - Channel Link Z - Data 3 - Input CC4 - Camera Control 4 - Output Yes
7, 20 TERM - Unused terminated input SERTC - Serial COM - Output Yes
9, 22 YCLK - Channel Link Y - Clock - Input XCLK - Channel Link X - Clock - Input  
12, 25 Y0 - Channel Link Y - Data 0 - Input X0 - Channel Link X - Data 0 - Input  
11, 24 Y1 - Channel Link Y - Data 1 - Input X1 - Channel Link X - Data 1 - Input  
10, 23 Y2 - Channel Link Y - Data 2 - Input X2 - Channel Link X - Data 2 - Input  
8, 21 Y3 - Channel Link Y - Data 3 - Input X3 - Channel Link X - Data 3 - Input  

See also: Camera Connectors

As shown in the above table, five pairs of pins of the Camera Link B connector change also their direction according to the configuration: they become outputs when 1628 Grablink Duo operates in the 2-camera Base configuration.

To prevent short-circuits, don't connect a Medium/72-bit/Full/80-bit configuration camera to Camera Link B connector when 1628 Grablink Duo operates in the 2-camera Base configuration.

NOTE: To prevent risk of short-circuits, 1628 Grablink Duo are configured at factory for 1-camera Medium/72-bit/Full/80-bit configuration.

Cable Requirements

● The camera cables must be terminated with a 26-pin Shrunk Delta Ribbon - SDR - connector at the frame grabber side
● Both PoCL and non-PoCL cables can be used.

The usage of poor quality Camera Link cables may cause malfunction. This becomes critical for systems with a high clock rate or with long cables length. Therefore, Euresys recommends using Camera Link cables that are certified by the cable manufacturer for the length vs. clock rate combination.

Power over Camera Link - PoCL

See also: Refer to Power over Camera Link in the Functional Guide