TTL Input/Output (Version 2)
TTL Input/Output Simplified schematic
The port implements a 3.3 V LVTTL driver and a 5 V-compliant 3.3 V LVTTL receiver.
DC characteristics
Parameter | Conditions | Min. | Typ. | Max. | Units |
---|---|---|---|---|---|
ESD protection | Human Body Model (HBM) | 2 | kV |
The I/O port includes a latch-up protection.
Driver
Parameter | Conditions | Min. | Typ. | Max. | Units |
---|---|---|---|---|---|
Low-level output current | 64 | mA | |||
Low-level output voltage | @ 8 mA | 0.34 | 0.36 | V | |
@ 16 mA | 0.48 | 0.55 | V | ||
@ 32 mA | 0.78 | 0.81 | V | ||
@ 64 mA | 1.34 | 1.36 | V | ||
High-level output current | -32 | mA | |||
High-level output voltage | @-8 mA; (1) | 2.60 | 3.00 | V | |
@-16 mA; (1) | 2.20 | 2.70 | V | ||
@-32 mA; (1) | 1.75 | 2.20 | V | ||
ESD protection | Human Body Model (HBM) | 2 | kV |
Condition (1): 300 Ohms line termination resistor to GND.
Receiver
Parameter | Conditions | Min. | Typ. | Max. | Units |
---|---|---|---|---|---|
Absolute maximum voltage rating | 0 | 5 | V |
AC characteristics
Driver
Parameter | Conditions | Min. | Typ. | Max. | Units |
---|---|---|---|---|---|
Pulse width | 100 | ns | |||
Pulse rate | 0 | 5 | MHz | ||
10%-90% rise time | 8 | ns | |||
10%-90% fall time | 7.5 | ns |
Receiver
Parameter | Conditions | Min. | Typ. | Max. | Units |
---|---|---|---|---|---|
Pulse width | 100 | ns | |||
Pulse rate | 0 | 5 | MHz |
Logical Map
The state of the port is reported as follows:
Input voltage | Logical State |
---|---|
VIN > 2.0 V | HIGH |
VIN < 0.8 V | LOW |
Unconnected input port | Undetermined |
Compatible sources
Sources with the following drivers are compatible:
□ | LVTTL ( 3.3 V low-voltage TTL) |
□ | TTL (5 V TTL) |
□ | CMOS (5 V CMOS) |
Compatible loads
Loads with the following receivers are compatible:
□ | LVTTL ( 3.3 V low-voltage TTL) |
□ | TTL (5 V TTL) |